Process for manufacturing an integrated CMOS circuit

ABSTRACT

In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is based on the problem of specifying an improvedmethod for producing an integrated CMOS circuit using dual work functiongate technology in which lateral dopant diffusion is suppressed andwhich can be carried out with reduced process complexity compared withknown solutions.

2. Description of the Prior Art

Both n-channel MOS transistors and p-channel MOS transistors are used inCMOS logic circuits; for example, in inventors. Electrical connectionsbetween gate electrodes of p-channel MOS transistors and n-channel MOStransistors are, in this case, very often realized in a gate plane whichis formed by structuring a layer and which comprises, in addition to thegate electrodes, connection elements between the gate electrodes. It isvery often the case that the gate electrodes and the connection elementsbetween the gate electrodes are formed as a continuous gate line. InCMOS circuits which are operated with a supply voltage of 5 volts, thegate structure is usually formed from n⁺ -doped polysilicon or polycide.

In CMOS circuits for low-voltage/low-power applications which areoperated with a supply voltage of <3 volts, the MOS transistors areoptimized such that they have threshold voltages |V_(th) |<0.5 volt inconjunction with low leakage currents. The associated high requirementson the short-channel behavior of the MOS transistors are satisfied bythe use of dual work function gate technology with an optimized gatework function. Dual work function gate technology is understood to meanthe fact that the gate electrode of the n-channel MOS transistors is n⁺-doped and the gate electrode of the p-channel MOS transistors is p⁺-doped. Owing to this different doping in the gate electrodes for then-channel MOS transistors and the p-channel MOS transistors, there isthe risk of lateral dopant diffusion in the case of a gate structurehaving a continuous gate line which connects differently doped gateelectrodes (see, for example, L. C. Parrillo, IEDM '85, p. 398).

The electrical properties, for example the threshold voltage V_(t) h, ofthe MOS transistors depend on the gate doping. Lateral dopant diffusionleads to a change in the gate doping and thus to undesirable,uncontrollable parameter shifts. In the extreme case, it is possible forreverse doping of the gate electrodes to occur, and hence total failureof the components. Furthermore, in the connection between n⁺ -doped gateelectrodes and p⁺ -doped gate electrodes, it is necessary, with regardto a low bulk resistance, that n⁺ -doped regions and p⁺ -doped regionsadjoin one another directly since otherwise a space charge zone forms.

In order to suppress lateral dopant diffusion in dual work function gatetechnology, it has been proposed (see, for example, D. C. H. Yu et al.,Int. J. High Speed Electronics and Systems, Vol. 5, p. 135, 1994) not touse any continuous connections made of polysilicon between differentlydoped gate electrodes in the gate plane. Instead, the gate line made ofpolysilicon is interrupted and is electrically conductively connectedvia a metal bridge made of aluminum, for example. As an alternative,after the interruption of the gate line, a suitable metallic conductor(TiN, WI WSi₂) is deposited and structured. This solution is complicatedand in some instances requires additional space for contact-making andmetallization.

Furthermore, it has been proposed (see C. Y. Wong et al., IEDM '88, p.238) to produce, in dual work function gate technology, planarsource/drain regions and the correspondingly doped gate electrodes byimplantation with the same dopant. For this purpose, the implantationsare carried out before the structuring of the gate electrodes. Withregard to planar source/drain regions, limitations must be observed inthe case of the implantation doses and the thermal loading. However,this leads to a narrow process window; for example, during dopantactivation in the gate electrode and during planarization reflow.

SUMMARY OF THE INVENTION

In a method according to the present invention, a polysilicon layerproduced for the purpose of forming the gate structure. The averagegrain diameter in the polysilicon layer is greater than the minimumextent in the gate plane. The invention makes use of the insight thatlateral dopant diffusion in the gate structure is principally caused bygrain boundary diffusion in the polycrystalline silicon. This grainboundary diffusion is extremely rapid. For example, boron diffusion inmonocrystalline silicon is less than along the silicon grain boundariesin polycrystalline silicon by a factor of 100 to 1000.

By using a polysilicon layer having an average grain diameter greaterthan the minimum dimensions in the gate structure, the grain boundarydensity in the region of the minimum dimensions in the polysilicon layeris drastically reduced in the method according to the present invention.In this region, diffusion takes place only in the silicon grains at adiffusion rate similar to that in monocrystalline silicon. Thepolysilicon layer is preferably produced by deposition of an amorphoussilicon layer and subsequent solid phase crystallization, as isdisclosed for example in S. Takenaka et al., SSDM '90, p. 955. Theminimum dimension may be the web width of the connection between twogate electrodes, for example.

A further improvement with regard to the suppression of lateral dopantdiffusion is obtained by a design measure in the gate structure. Whenthe polysilicon layer is structured, a constriction is created in theconnection between gate electrodes of n-channel and p-channel MOStransistors. The width of the connection in the region of theconstriction is smaller than outside the latter and less than theaverage grain diameter of the polysilicon layer. The constriction ispreferably situated in the region in which n⁺ -doped polysilicon adjoinsp⁺ -doped polysilicon.

The invention utilizes the fact that the diffusion in the silicon grainstakes place in a manner corresponding to the diffusion inmonocrystalline silicon, and is thus greatly reduced in comparison withdiffusion via grain boundaries. Since the average grain size of thepolysilicon layer is greater than the smallest dimension in the gatestructure, diffusion can take place only in the silicon grains at thislocation of the smallest dimension, since there is no grain boundaryhere.

The integrated CMOS circuit is preferably formed in a semiconductorsubstrate having monocrystalline silicon at least in the region of theCMOS circuit. In this case, the semiconductor substrate may be either amonocrystalline silicon wafer or a monocrystalline silicon layer of anSOI substrate.

Insulation structures for defining the active regions for the n-channelMOS transistor and the p-channel MOS transistor are formed in thesemiconductor substrate. These insulation structures are formed using aLOCOS method with regard to customary logic processes. However, theinsulation structures can also be formed in a different way, for exampleby means of a trench filled with insulating material.

It lies within the scope of the present invention to produce a p-dopedwell in the active region for accommodating the n-channel MOS transistorand an n-doped well in the active region for accommodating the p-channelMOS transistor.

Additional features and advantages of the present invention aredescribed, and will be apparent from, the detailed description of thepresently preferred embodiments and from the drawings.

DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a substrate with insulation structures for defining activeregions for an n-channel MOS transistor and a p-channel MOS transistorafter the formation of correspondingly doped wells.

FIG. 2 shows the substrate of FIG. 1 after the formation of a gate oxideand the deposition of an amorphous silicon layer.

FIG. 3 shows the substrate of FIG. 2 after the formation of apolysilicon layer by crystallization of the amorphous silicon layer.

FIG. 4 shows a plan view of the substrate of FIG. 3 after the formationof a gate structure by structuring the polysilicon layer.

FIG. 5 shows a cross section along lines V--V of FIG. 4 through thesemiconductor substrate after the structuring of the polysilicon layerand of the gate oxide.

FIG. 6 a cross section along lines VI--VI of FIG. 4 through thesemiconductor substrate after the formation of spacers and reoxidation.

FIG. 7 and FIG. 8 show mutually perpendicular sections along linesVII--VII and VIII--VIII respectively, of FIG. 4 through thesemiconductor substrate after p-ion implantation.

FIG. 9 and FIG. 10 show mutually perpendicular sections along linesIX--IX and X--X, respectively, of FIG. 4 through the semiconductorsubstrate after n-ion implantation.

FIG. 11 and FIG. 12 show mutually perpendicular sections along linesXI--XI and XII--XII, respectively, of FIG. 3 through the semiconductorsubstrate after the completion of an n-channel MOS transistor and of ap-channel MOS transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In a substrate 1 made of monocrystalline silicon, for example, fieldoxide regions 2 which define an active region 4a for a p-channel MOStransistor and an active region 4b for an n-channel MOS transistor areproduced using a LOCOS method, (see FIG. 1). An n-doped well 3a isproduced in the active region 4a for the p-channel MOS transistor. Ap-doped well 3b is produced in the active region 4b for the n-channelMOS transistor. The field oxide regions 2 and the wells 3a, 3b areproduced according to process steps which are customary in CMOStechnology. A dopant concentration of 1×10¹⁷ P/cm³, for example, is setin the n-doped well 3a, and a dopant concentration of 1×10¹⁷ B/cm³, forexample, is set in the p-doped well 3b.

A gate oxide 5 is grown to a thickness of 3 to 10 nm, for example, bymeans of thermal oxidation at 900° C., (see FIG. 2). An amorphoussilicon layer 6a is subsequently deposited over the whole area. Theamorphous silicon layer 6a is deposited using low temperature depositionat a temperature of below 500° C., preferably in the range of 0.1-10torr using disilane (Si₂ H₆). This low temperature deposition processhas the advantage over an SiH₄ process in that the amorphous siliconlayer 6a exhibits an improved crystallization behavior. The amorphoussilicon layer 6a is produced either without doping or with a slightdoped with a dopant concentration of less than 5×10¹⁹ cm⁻³ with a layerthickness of 50 to 500 nm.

The amorphous silicon layer 6a is subsequently converted into apolysilicon layer 6b by crystallization at a low temperature, preferablybetween 600° and 800° C. (see FIG. 3). The polycrystalline silicon layer6b is composed of large-grain polysilicon with an average grain size <L>of preferably >200 nm. The average grain size <L> can be set by way ofthe heat-treatment conditions, that is to say temperature and durationof the crystallization. With heat-treatment conditions of 600° C., 8hours, it is possible to obtain an average grain size of several μm. Thepolysilicon layer 6b is structured with the aid of aphotolithographically produced mask and an etching technique; forexample by means of anisotropic etching using HBr/Cl₂ gas. A gatestructure 6c, which includes, in addition to undoped gate electrodes 7for the p-channel MOS transistor and the n-channel MOS transistor, aconnection 70 between the two gate electrodes 7, is formed in theprocess. The connection 70 includes a constriction 89 at which the widthof the connection 70 is reduced. The width 8 is 250 nm, for example, inthe region of the constriction 89. Outside the constriction 89, thewidth of the connection 70 corresponds to the width 7a, 7b of the gateelectrodes 7, which is equal to the gate length of the p-channel MOStransistor and of the n-channel MOS transistor, respectively (see FIG.4).

The width 8 of the constriction 89 is set such that it is smaller,preferably significantly smaller, than the average grain size <L>. Thelength 9 of the constriction 89, on the other hand, is set such that itis greater than the average grain size <L> of the polysilicon. It isensured in this way that lateral dopant diffusion takes place almostexclusively in the silicon grains in the region of the constriction 89.The width 8 and the length 9 of the constriction 89 are set independence on the polysilicon grain size, the thermal budget as well ason boundary conditions relating to design and lithography. At an averagegrain size <L> of 400 nm, for example, the width 8 is 250 nm, the length9 is 800 nm and the gate length 7a, 7b is 1 μm,

The undoped gate electrodes 7 are subsequently provided with SiO₂spacers 10 by means of conformal deposition of an SiO₂ layer andanisotropic etching back of the SiO₂ layer using CHF₃ /Ar, for example.A thermal oxide layer 11 is produced to a thickness of 15 nm on exposedsilicon surfaces by means of thermal oxidation at 900° C., for example(see FIG. 6).

A photoresist mask 12, which covers the active region 4b for then-channel MOS transistor, is subsequently produced with the aid ofphotolithographic process steps (see FIG. 7). In this case, thephotoresist mask 12 reaches as far as the adjacent field oxide regions2. The photoresist mask 12 reaches right into the region of theconstriction 89 (see FIG. 8). A p⁺ -doped gate electrode 14 and alsop-doped source/drain regions 15a are produced for the p-channel masstransistor by means of ion implantation 13 with boron or BF₂ with a doseof 5×10¹⁵ at/cm², for example, and an energy of, for example, 15 and 40keV, respectively. At the same time, that part of the connection 70which is not covered by the photoresist mask 12 is p⁺ -doped.

After the removal of the resist mask 12, a photoresist mask 16 isproduced which covers the region for the p-channel MOS transistor (seeFIG. 9). In the region of the connection 70, the photoresist mask 16reaches as far as the constriction 89 (see FIG. 10). An n⁺ -doped gateelectrode 18a and also n-doped source/drain regions 19a are formed bymeans of implantation 17 with arsenic or phosphorus with a dose of5×10¹⁵ at/cm² and an energy of 60 and 120 keV, respectively. During theimplantation 17, that part of the connection 70 and of the constriction89 which is not covered by the photo-resist mask 16 is n⁺ -doped.

The photoresist mask 16 is subsequently removed.

The implanted dopant is electrically activated by subjecting thesubstrate 1 to a heat treatment. p-doped source/drain diffusion regions15b and n-doped source/drain diffusion regions 19b are formed in theprocess.

Furthermore, a p-doped gate 14b is produced for the p-channel MOStransistor and an n-doped gate 18b is produced for the n-channel MOStransistor (see FIG. 11 and FIG. 12).

The thermal SiO₂ layer 11 is removed by wet-chemical means, for exampleusing HF/HNO₃. Afterwards, a metallic conductor 20 is appliedselectively to exposed silicon areas, that is to say on the surface ofthe n-doped and, respectively, p-doped source/drain diffusion regions15b, 19b and on the n-doped and, respectively, p-doped gate 18b, 14b.The metallic conductor 20 may be formed from TiSi₂ using a salicidemethod, for example. Furthermore, the metallic conductor 20 may beapplied by selective deposition of tungsten using a CVD method. Themetallic conductor 20 also extends over the connection 70 with theconstriction 89. n⁺ -doped and p⁺ -doped regions of the connection 70adjoin one another in the region of the constriction 89. The metallicconductor 20 runs over this boundary and connects the n⁺ -doped regionsof the connection 70 to the p⁺ -doped regions.

Owing to the grain size of the polysilicon layer, no appreciable lateraldiffusion occurs during the heat treatment for activating the dopant inthe region of the constriction 89. A well-defined boundary between n⁺-doped and p⁺ -doped regions of the connection 70 is preserved in theregion of the constriction 89. The p⁺ -doped gate 14b is connected tothe n⁺ -doped gate 18b. The structure constitutes an invertor.

The circuit arrangement is completed by the deposition of a layer ofborophosphorus silicate glass and planarization, also by etching contactholes and metallization (not specifically illustrated).

Although the present invention has been described with reference tospecific embodiments, those skilled in the art will recognize thatchanges may be made thereto without departing from the spirit and scopeof the invention as set forth in the hereafter appended claims.

We claim:
 1. A method for producing an integrated CMOS circuit,comprising the steps of:producing insulation structures in asemiconductor substrate, wherein each structure defines active regionsfor at least one n-channel MOS transistor and one p-channel MOStransistor; forming n-doped source/drain regions for the at least onen-channel MOS transistor; forming p-doped source/drain regions for theat least one p-channel MOS transistor; forming a gate oxide over theinsulation structures; producing a polysilicon layer over the gateoxide; forming a gate structure by structuring the polysilicon layer,the gate structure including a first gate electrode for the n-channelMOS transistor and a second gate electrode for the p-channel MOStransistor as well as a connection between the first and second gateelectrodes; providing at least a surface of the gate structure with ametallic conductor; and wherein the polysilicon layer is produced with agrain size such that an average grain diameter is greater than a widthof a narrowed or constriction part of the connection between the firstand second gate electrodes of the gate structure and wherein the firstgate electrode is n-doped and the second gate electrode is p-doped.
 2. Amethod for producing an integrated CMOS circuit as claimed in claim 1,further comprising the step of:depositing an amorphous silicon layerover the gate oxide for the purpose of forming the polysilicon layer bycrystallization in a heat treatment step.
 3. A method for producing anintegrated CMOS circuit as claimed in claim 2, further comprising thesteps of:depositing the amorphous silicon layer using Si₂ H₆ as processgas in a temperature range between 400° C. and 500° C.; and carrying outthe heat-treatment step for crystallization in a temperature rangebetween 600° C. and 800° C.
 4. A method for producing an integrated CMOScircuit as claimed in claim 1, further comprising the step of:providingthe connection between the first and second gate electrodes with aconstriction part.
 5. A method for producing an integrated CMOS circuitas claimed in claim 1, further comprising the steps of:effecting thedoping of the first gate electrode by implantation with n-doping ions,the n-doped source/drain regions being formed simultaneously; andeffecting the doping of the second gate electrode by implantation withp-doping ions, the p-doped source/drain regions being formedsimultaneously.
 6. A method for producing an integrated CMOS circuit asclaimed in claim 1, further comprising the step of:forming theinsulation structures using a LOCOS method.
 7. A method for producing anintegrated CMOS circuit as claimed in claim 4, further comprising thesteps of:producing a p-doped well in the active region for forming then-channel MOS transistors; and producing an n-doped well in the activeregion for forming the p-channel MOS transistors.